Giovanni De Micheli
Researcher Next ID · RN-034037
Researcher · Computer Science
École Polytechnique Fédérale de Lausanne
Lausanne, Switzerland
- Works count
- 1,125
- Citation count
- 35,331
- H-index
- 87
- i10-index
- 548
Research interests
Publications
Majority-Inverter Graph: A New Paradigm for Logic Optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2015 · https://doi.org/10.1109/tcad.2015.2488484
Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs
Journal · 2012 · https://doi.org/10.1109/iedm.2012.6479004
Synchronous versus asynchronous modeling of gene regulatory networks
Bioinformatics · 2008 · https://doi.org/10.1093/bioinformatics/btn336
Networks on Chips: Technology and Tools
CERN Document Server (European Organization for Nuclear Research) · 2006
Designing application-specific networks on chips with floorplan information
Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design · 2006 · https://doi.org/10.1145/1233501.1233573
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
IEEE Transactions on Parallel and Distributed Systems · 2005 · https://doi.org/10.1109/tpds.2005.22
Analysis of error recovery schemes for networks on chips
IEEE Design & Test of Computers · 2005 · https://doi.org/10.1109/mdt.2005.104
Error control schemes for on-chip communication links: the energy-reliability tradeoff
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2005 · https://doi.org/10.1109/tcad.2005.847907
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Design, Automation, and Test in Europe · 2004 · https://doi.org/10.5555/968879.969208
SUNMAP
Journal · 2004 · https://doi.org/10.1145/996566.996809
Bandwidth-constrained mapping of cores onto NoC architectures
Journal · 2004 · https://doi.org/10.5555/968879.969207
Bandwidth-constrained mapping of cores onto NoC architectures
Journal · 2004 · https://doi.org/10.1109/date.2004.1269002
Networks on chips: a new SoC paradigm
Computer · 2002 · https://doi.org/10.1109/2.976921
Analysis of power consumption on switch fabrics in network routers
Proceedings - ACM IEEE Design Automation Conference · 2002 · https://doi.org/10.1145/513918.514051
Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems
Journal · 2002 · https://doi.org/10.1109/glsv.1997.580414
Dynamic voltage scaling and power management for portable systems
Journal · 2001 · https://doi.org/10.1145/378239.379016
System-level power optimization
ACM Transactions on Design Automation of Electronic Systems · 2000 · https://doi.org/10.1145/335043.335044
Dynamic power management for portable systems
Journal · 2000 · https://doi.org/10.1145/345910.345914
Policy optimization for dynamic power management
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1999 · https://doi.org/10.1109/43.766730
Cycle-accurate simulation of energy consumption in embedded systems
Journal · 1999 · https://doi.org/10.1145/309847.310090
Dynamic Power Management
Journal · 1998 · https://doi.org/10.1007/978-1-4615-5455-4
Dynamic Power Management: Design Techniques and CAD Tools
CERN Document Server (European Organization for Nuclear Research) · 1997
Automatic synthesis of low-power gated-clock finite-state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1996 · https://doi.org/10.1109/43.503933
Hardware-software cosynthesis for digital systems
IEEE Design & Test of Computers · 1993 · https://doi.org/10.1109/54.232470
Optimal State Assignment for Finite State Machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1985 · https://doi.org/10.1109/tcad.1985.1270123
Current projects
No projects listed.