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Chip-Hong Chang

Researcher Next ID · RN-036886

Researcher · Computer Science

Nanyang Technological University

Singapore, Singapore

Accepting doctoral researchersFunding unknown
Works count
632
Citation count
8,582
H-index
48
i10-index
181

Research interests

Computer Science
Engineering
Physical Unclonable Functions (PUFs) and Hardware Security
Low-power high-performance VLSI design
Integrated Circuits and Semiconductor Failure Analysis
Digital Filter Design and Implementation
Coding theory and cryptography

Publications

  • Halide perovskite memristors as flexible and reconfigurable physical unclonable functions

    Nature Communications · 2021 · https://doi.org/10.1038/s41467-021-24057-0

  • An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2020 · https://doi.org/10.1109/tcad.2020.3047976

  • Reliable and Modeling Attack Resistant Authentication of Arbiter PUF in FPGA Implementation With Trinary Quadruple Response

    IEEE Transactions on Information Forensics and Security · 2018 · 10.1109/tifs.2018.2870835

  • A Retrospective and a Look Forward: Fifteen Years of Physical Unclonable Function Advancement

    IEEE Circuits and Systems Magazine · 2017 · https://doi.org/10.1109/mcas.2017.2713305

  • Residue Number Systems: A New Paradigm to Datapath Optimization for Low-Power and High-Performance Digital Signal Processing Applications

    IEEE Circuits and Systems Magazine · 2015 · 10.1109/mcas.2015.2484118

  • A Low-Power Hybrid RO PUF With Improved Thermal Stability for Lightweight Applications

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2015 · 10.1109/tcad.2015.2424955

  • Exploiting Process Variations and Programming Sensitivity of Phase Change Memory for Reconfigurable Physical Unclonable Functions

    IEEE Transactions on Information Forensics and Security · 2014 · 10.1109/tifs.2014.2315743

  • A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm2 SRAM cell size in a 291Mb array

    · 2008 · 10.1109/iedm.2008.4796777

  • An Area Efficient 64-bit Square Root Carry-select Adder for Low Power Applications

    · 2005 · 10.1109/iscas.2005.1465528

  • A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2005 · https://doi.org/10.1109/tvlsi.2005.848806

  • Ultra Low-Voltage Low-Power CMOS 4-2 and 5-2 Compressors for Fast Arithmetic Circuits

    IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · 2004 · https://doi.org/10.1109/tcsi.2004.835683

  • A novel hybrid pass logic with static CMOS output drive full-adder cell

    · 2003 · 10.1109/iscas.2003.1206266

  • An efficient reverse converter for the 4-moduli set [2/sup n/ - 1, 2/sup n, 2/sup n + 1, 2/sup 2n/ + 1] based on the new chinese remainder theorem

    IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · 2003 · 10.1109/tcsi.2003.817789

Current projects

    No projects listed.